1. Field
The present invention relates to a display device, and particularly to a structure of an active matrix display device comprising a thin film transistor and a storage capacitor, and also to a method of producing it.
2. Description of the Related Art
A liquid crystal display device (LCD) which is one of conventional usual thin panels is generally used as a monitor for a personal computer, that for a portable information terminal, and the like, while taking advantage of low power consumption, small size, and light weight. Recently, such a device is widely used in a TV set, and will replace a conventional cathode-ray tube. Also an electroluminescence EL display device in which a luminous body such as an EL element is employed in a pixel display portion is used as a next-generation panel device. In such an EL element, problems of an LCD such as restrictions of view angle and contrast and difficulty of followability of high-speed response to a motion picture can be solved, and features which an LCD does not have, such as the self-luminous type, wide view angle, high contrast, and high-speed response are advantageously used.
In a pixel region of such a display device, a switching element such as a thin film transistor (TFT) is formed. An example of frequently employed TFTs is a TFT having a MOS structure using a semiconductor film. As structures of TFTs, there are several kinds including the inverse staggered type and the top-gate type. Semiconductor films such as a silicon film are classified into types including an amorphous semiconductor film and a polycrystalline semiconductor film. The kinds and types are adequately selected in accordance with the use and performance of a display device. In a panel of a medium or large size, a thin film transistor using an amorphous semiconductor film (a-Si TFT) is used. By contrast, in a panel of a small size, it is often to use a polycrystalline semiconductor film which enables miniaturization of a TFT because the aperture ratio of a display region can be increased.
Namely, the use of a thin film transistor using a polycrystalline semiconductor film (LTPS-TFT) in a display region can reduce not only the capacity of a switching transistor in each pixel, but also the area of a storage capacitor connected to the drain side, whereby a liquid crystal display device of a high resolution and a high aperture ratio can be realized. When LTPS-TFTs are used in a circuit in the periphery of a display device in addition to a display region, the numbers of ICs and substrates on which ICs are mounted can be reduced, and the periphery of the display device can be simplified. Therefore, a highly reliable display device having a narrow frame can be realized. An LTPS-TFT plays a leading role in a high-resolution liquid crystal display device such as QVGA (pixel number: 240×320) or VGA (pixel number: 480×640) for a panel which is as small as that for a portable telephone. As described above, an LTPS-TFT is largely superior in performance than an a-Si TFT, and its resolution is expected to be further advanced.
As a method of producing a polycrystalline semiconductor film that is to be used in an LTPS-TFT, a method is known in which an amorphous semiconductor film is first formed above a silicon oxide film or the like that is formed as a foundation film on a substrate, and thereafter the semiconductor film is irradiated with a laser beam to be formed as a polycrystalline film. Also a method is known in which a TFT is produced after such a polycrystalline semiconductor film is produced. Specifically, a gate insulating film made of a silicon oxide film is first formed on a polycrystalline semiconductor film formed on a substrate, and a gate electrode is formed. Thereafter, impurities such as phosphorus or boron are introduced into the polycrystalline semiconductor film via the gate insulating film with using the gate electrode as a mask. By this way, source/drain regions are formed. Then, an interlayer insulating film is formed so as to cover the gate electrode and the gate insulating film, and thereafter contact holes which reach the source/drain regions are opened in the interlayer insulating film and the gate insulating film. A metal film is formed on the interlayer insulating film, and patterned so that the metal film is connected to the source/drain regions through the contact holes, thereby forming source/drain electrodes (for example, see Patent References 1 and 2). Thereafter, a pixel electrode or a self-luminous element is formed to be connected to the drain electrode, with the result that an active matrix display device is formed.
As an LTPS-TFT, a TFT of the top-gate type which is described above is usually employed. In such a TFT, as a gate insulating film, a silicon oxide film is formed in a very thin thickness of about 100 nm to be sandwiched between a gate electrode and a polycrystalline semiconductor film, thereby forming a MOS structure. Since the thickness of the silicon oxide film is very small, there is a further advantage that, when the film is used also as a dielectric insulating film of a storage capacitor which is formed simultaneously with the TFT, the area of the storage capacitor can be reduced. In this case, the storage capacitor is formed in the following manner. First, impurities such as phosphorus or boron are introduced into the polycrystalline semiconductor film which is below the gate insulating film, to lower the resistance. Thereafter, a conductive film pattern is formed on the gate insulating film so as to be opposed to the polycrystalline semiconductor film in which the resistance is lowered, via the gate insulating film (for example, see Patent Reference 3).
With respect to a storage capacitor which is placed for each pixel in an active matrix display device, the structure in the case of an LTPS-TFT is largely different from that in the case of an a-Si TFT. In the case where a storage capacitor is formed simultaneously with an LTPS-TFT, the portion corresponding to the lower electrode is the polycrystalline semiconductor film in which the resistance is lowered, and that corresponding to the dielectric insulating film is the gate insulating film in which the thickness is very small. By contrast, in the case where a storage capacitor is formed simultaneously with an a-Si TFT, usually, a structure is employed in which metal films respectively used as gate and source wirings sandwich an insulating film having a thickness of about 300 to 700 nm. As described above, the required area of the storage capacitor in the case of an LTPS-TFT is smaller.
In the case of an LTPS-TFT, however, the portion constituting one of the electrodes of the storage capacitor is not a metal film, but a polycrystalline semiconductor film. Hence, there is a problem in which a resistance of the polycrystalline semiconductor film is high. Usually, the resistance is lowered by introducing impurities such as phosphorus. Even when this process is performed, the resistance can be lowered at the most to only several kΩ/□ in the term of a sheet resistance conversion. Therefore, a large problem arises when, for example, a wiring is drawn from the TFT to the storage capacitor. Furthermore, a voltage dependency due to the property of the semiconductor possessed by the polycrystalline semiconductor film itself is produced. Consequently, there is a further problem in that a desired capacitance corresponding to the thickness of the insulating film cannot be obtained, and the display quality of the active matrix display device is lowered. In order to solve these problems, for example, it may be contemplated to employ a technique in which a conductive film made of a metal or the like is formed below the polycrystalline semiconductor film. In the crystallization of a semiconductor film by a high-temperature treatment using a laser beam or the like, however, the conductive film adversely affects the crystallization, and a polycrystalline semiconductor film of the high quality cannot be obtained. In the view of this point, the technique is not practical (for example, see Patent Reference 4).
[Patent Reference 1] JP-A-2003-75870 (FIG. 1)
[Patent Reference 2] JP-A-H11-261076 (FIG. 1)
[Patent Reference 3] JP-A-2000-206566 (FIG. 1)
[Patent Reference 4] JP-A-H10-177163 (FIG. 10)